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Principal Digital Design & Verification Engineer Negotiable Collect Apply
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Principal Digital Design & Verification Engineer

Annual Salary Negotiable

Professionals - Business and Systems Analysts, and Programmers

NSW - Other Regional (Post code: 2000)

Recruiting numbers: 1

Expiration date: 27-Mar-2023

Full Time
27-Feb-2023 update visited:
Job requirements

Educational requirements: Bachelor

English requirements: Competent English

Requirements for skilled employment experience for years: 1-3 years

Required residence status: Temporary visa, Permanent resident, Citizen

Accept remote work: unacceptable

We are open to sponsoring a work visa for the right candidate. Responsibilities include: Chip and block design and verification Enhancement of our design and verification infrastructure Working across teams to ensure efficient hardware-software co-design and implementation Working with, or taking on the role of, a chip lead and assisting with tapeout duties such as system verification, synthesis, ensuring excellent - QoR in P&R, gate level netlist simulations to validate design and power intent, and power analysis Delivery of large complex projects on time Mentoring of junior team members What we’re looking for: Digital design and verification experience with 15+ years relevant industry experience MSc in Electrical / Electronics / Communication Engineering or Computer Science A deep understanding of digital design fundamentals including low power and multi-clock-domain design for mass-produced, mixed-signal chips Expert in mixed signal ASIC design and simulation, experience with AMS simulation is a plus Very experienced with the Cadence or Synopsys simulation suites Experience with coverage collection tools Experience defining functional verification requirements, implementing tests to meet them Expert in HDL languages such as Verilog, SystemVerilog or VHDL Experience with building complex testbench infrastructures Experience running and debugging gate level simulations in post-PnR netlists with SDF annotation, power-aware simulation experience is a plus Experience setting up and maintaining continuous integration (CI) flows for regression testing and reporting status A good understanding of embedded processor systems, familiarity with RISC-V is a plus Experience writing embedded C and structuring code in a way which makes reusability and maintenance a breeze Experience with cocotb is a plus -Hands-on experience with Linux development environment staples such as make, shell scripts and Python Experience using the git revision control tool Check out what it is like to work for us: https://youtu.be/9jzHB8M_iDYOpens in new window or tab
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Last online time: 19-Jan-2024 11:28
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